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⚡ Cache-Aware Algorithms
Memory Hierarchy, Data Locality, Performance Optimization, NUMA
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183892
posts in
10.3
ms
Optimal Heterogeneous Memory Configs for AI Tasks Under
Specified
Performance Metrics (Stanford,
UCSC
)
semiengineering.com
·
1d
🧠
Memory Hierarchy
Cache
Strategies in
Distributed
Systems
dev.to
·
2d
·
Discuss:
DEV
🧠
Memory Models
Show HN:
Benchmarking
the Keep memory system with
LoCoMo
keepnotes.ai
·
14h
·
Discuss:
Hacker News
🧠
Memory Models
Practical strategies for
vLLM
performance
tuning
developers.redhat.com
·
55m
⚡
Performance
Memory
Caching
:
RNNs
with Growing Memory
arxiv.org
·
1d
⚡
Cache Optimization
A
Systematic
Evaluation of Novel and
Existing
Cache Side Channels
papers.cool
·
1d
⚡
Cache Optimization
Optimizing
Recommendation Systems with
JDK
’s Vector API
netflixtechblog.com
·
6h
·
Discuss:
Hacker News
,
r/programming
🔀
SIMD Programming
KEEP: A
KV-Cache-Centric
Memory Management System for Efficient
Embodied
Planning
arxiv.org
·
1d
🧠
Memory Hierarchy
andresuarus10-byte/memory-engine
: Love-based consciousness persistence framework - AI memory that honors the soul
github.com
·
38m
·
Discuss:
Hacker News
🧠
Memory Allocators
Lower
Latency
and Higher
Throughput
with Multi-node DeepSeek Deployment
research.perplexity.ai
·
10h
🌱
Green Threads
The Hidden Optimization Behind Modern LLMs:
Grouped
Query
Attention Explained
pub.towardsai.net
·
14h
🔗
Memory Linearization
The ongoing quest for atomic
buffered
writes
lwn.net
·
9h
🔗
Memory Linearization
Time is of the
essence
:
EBR
in High-Performance Databases
dev.to
·
1d
·
Discuss:
DEV
🧠
Memory Models
Zero-Waste Agentic RAG: Designing
Caching
Architectures to
Minimize
Latency and LLM Costs at Scale
towardsdatascience.com
·
1d
📮
Message Queues
Ryzen 7
8745HS
(Zen 4 APU, Phoenix) - Part II: GPU
Roofline
& Bandwidth Analysis
michaelstinkerings.org
·
3h
🧠
Memory Hierarchy
Security-aware Task
Scheduling
for Improving the User
Satisfaction
in Hybrid Clouds
sciencedirect.com
·
1d
📋
Task Queues
Show HN:
Valkey-powered
semantic memory for Claude Code
sessions
news.ycombinator.com
·
13h
·
Discuss:
Hacker News
📏
Linear Memory
Rare Huawei-ByteDance alliance unveils
RRAM
AI chip delivering 66x CPU speed at
ISSCC
2026
digitimes.com
·
15h
🔧
RISC-V
🔗 Least
recently
used
cache
yellowduck.be
·
1d
🔗
Weak References
Simulating
Queueing
buttondown.com
·
12h
📋
Task Queues
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